The invention pertains to ECL gates for use in a variety of applications, and, more particularly, to ECL gates with switchable load impedances.
ECL gates are very popular in logic design because they are current mode logic devices where the bipolar transistors do not saturate. Because the transistors do not saturate, the switching times of such gates are very fast. The price for this increased speed of switching is large power consumption. That is, ECL gates draw large amounts of quiescent collector current even when they are not switching.
In complex computers and large memories, the amount of power an individual gate draws is critical to the overall system, because thousands of such gates are in use. Because of the large number of gates needed and the need for high speeds, the integrated form of gate is preferred for cost reasons and ECL gates are preferred for speed reasons.
ECL is a high speed logic form because saturation is avoided in the switching transistors. Further, the typically low logic swings reduce the charge required to change the voltage level of the various parasitic capacitances in the system. The typically low logic swings still give acceptable noise margins because of the inherently differential nature of ECL which allows first order cancellation of component variables such as Vbe etc. The disadvantage of standard ECL is that the power dissipation is quite high because the d.c. and transient power is the same. In large systems, the available power per gate is limited because the large number of gates require massive, complex and expensive power supplies and cooling equipment. The cooling equipment is required to minimize system and chip temperatures. High chip temperatures degrade component parameters and make it more difficult to keep the transistors out of saturation. High chip temperatures degrade system reliability because of the temperature dependence of several failure modes such as metal migration.
Large systems therefore have power budgets, and the designer must make power versus speed tradeoffs to meet the power budget.
Where power is limited, the capacitances in the ECL circuit cannot be charged and discharged as rapidly as in situations where unlimited current is available. This equates to lower circuit switching speed and lower system performance. Therefore, a need has arisen for an ECL gate which can operate in a high power consumption, high current mode for very rapid switching, but which can be switched to a low power consumption mode when the gate is not actively involved in performing its logic function.